Think in gates.
Write in Verilog.
Grow without limits.

1module counter_4bit (
2  input  wire       clk,
3  input  wire       rst,
4  output reg  [3:0] count
5);
6  always @(posedge clk) begin
7    if (rst)
8      count <= 4'b0;
9    else
10      count <= count + 1'b1;
11  end
12endmodule